Important Information for Proposers

A revised version of the NSF Proposal & Award Policies & Procedures Guide (PAPPG) (NSF 22-1), is effective for proposals submitted, or due, on or after October 4, 2021. Please be advised that, depending on the specified due date, the guidelines contained in NSF 22-1 may apply to proposals submitted in response to this funding opportunity.

Dear Colleague Letter

Supplements for Access to Semiconductor Fabrication (ASF)

Invites supplemental funding requests from current awardees of NSF's ENG or CISE directorates or NSF’s Division of Materials Research to support fabrication of research devices and systems through standard semiconductor fabrication facilities.

Dear Colleague:

With this Dear Colleague Letter (DCL), the National Science Foundation's Directorate for Engineering (ENG), the Directorate for Computer and Information Science and Engineering (CISE), and the Directorate for Mathematical and Physical Sciences (MPS) wish to notify the community of a new supplement program that will support access to semiconductor fabrication for principal investigators (PIs) of currently active awards in ENG, CISE, and Divisions of Materials Research (DMR) and Chemistry (CHE) in MPS. These supplemental funding requests are specifically targeted to support fabrication of research devices and systems through standard semiconductor fabrication facilities. The award supplements must be justified with a plan that includes specific fabrication parameters. Prospective PIs are encouraged to contact the cognizant Program Director prior to submission.


NSF has a long history of supporting basic research that has provided the underlying knowledge and innovation for the Nation's computing, sensing, and communication infrastructures based on semiconductor electronics. This infrastructure is the foundation of current enabling technologies, such as 5G communications, artificial intelligence, high-performance computing, advanced computer architecture, security, local and remote sensing, and other technologies. The ENG, CISE, and MPS Directorates also have a long history of funding basic semiconductor research and educating students with the skills and knowledge necessary to strengthen the semiconductor industry. ENG, CISE, and MPS researchers have demonstrated and evaluated their research through fabrication and testing of devices, and systems using a wide variety of semiconductor fabrication facilities.

However, in recent years the US has seen a sharp decline in the number of research devices and systems fabricated and tested. While simulations and emulations can provide detailed information, there is still great value in building and measuring real devices and systems, both in terms of research results and in educating a new generation of researchers and designers that can explore and exploit advanced semiconductor-based technologies and systems. The design of semiconductor integrated circuits and systems has become easier than ever before, given the wide and relatively affordable availability of industry-standard electronic design automation (EDA) tools, a recently emerging slate of open-source EDA tools, and a growing set of intellectual property (IP) in the form of design infrastructure. However, fabrication of these designs has become less frequent for a variety of reasons. This ASF supplement DCL is designed to address one aspect of this challenge through supplemental funding specifically to support fabrication of research devices and systems through standard semiconductor fabrication facilities.


PIs of currently active NSF awards within the Electrical, Communications, and Cyber Systems (ECCS) Division, the Civil, Mechanical and Manufacturing Innovation (CMMI) division, the Engineering Education and Centers (EEC) division or any of the other participating CISE (Computer and Network Systems [CNS], Computing and Communication Foundations [CCF]) and MPS (DMR, CHE) divisions and programs may propose supplemental funding requests to support specifically the fabrication of semiconductor devices and systems developed in their research projects. Supplemental funding awarded pursuant to this DCL may be used to support fabrication at any fabrication facility of the researcher's choice. There are many services specifically designed to support low-volume research fabrication by researchers and educators. A few of these services are listed here, but this is not meant to be a comprehensive list, nor is it implied that NSF is showing any preference or endorsement for one service provider over another. This is simply a list of some of the available alternatives.

  • MUSE is a company focused on providing multi-project wafer (MPW) services to university researchers. MUSE offers access to Taiwan Semiconductor Manufacturing Company (TSMC) CMOS processes with die sizes and quantities smaller than the requirements directly from TSMC. Shared block tape-outs on specific processes take these minimum sizes and quantities even further.
  • eFabless provides prototyping access to CMOS processes through Skywater Technologies. In addition to general MPW services, the eFabless ChipIgnite program provides a design-friendly framework in an affordable legacy process.
  • Google, through a partnership with eFabless, provides free fabrication access for open-source designs using open-source tools.
  • MOSIS is a service housed in the University of Southern California's Information Sciences Institute (ISI). It provides MPW services in a variety of semiconductor processes from TSMC, Intel, and Global Foundries.
  • Global Foundries provides an MPW service on many of their fabrication processes including different CMOS processes and silicon optical processes.
  • Many NSF researchers have worked with IMEC in Belgium to have designs fabricated in processes that include those from TSMC, ONSemi, UMC, and xFab, as well as the IMEC advanced 300-mm fabrication facilities.


PIs interested in submitting supplemental funding requests in response to this DCL should contact cognizant program officers prior to submission. All supplemental funding requests will be subject to the NSF's merit review process, as described in the NSF Proposal and Award Policies and Procedures Guide (PAPPG). Each NSF supplemental funding request must follow the guidance specified in the PAPPG Chapter VI.E.5 which includes the following sections: 1) a summary of the proposed work, and 2) justification of the need for supplemental funds. The content in the supplemental funding request should be organized by addressing the following items:

  • Summary of the research in the current NSF award, including original research vision, goals, activities, and accomplishments, spanning Intellectual Merit and Broader Impacts;
  • PIs must clearly explain how the proposed fabrication work is relevant and important to the current NSF award;
  • A summary of the proposed design to be fabricated. The PIs must include a short description of the design and its place in the research project. This should include details of the EDA tools and IP used, the size of the anticipated fabricated device/system, the semiconductor process being targeted, and the service provider being used to coordinate the fabrication of the project;
  • A budget and its justification for the fabrication of the device/system;

This supplemental funding opportunity is specifically for semiconductor fabrication, and not for board-level or system-level implementations. PIs interested in submitting supplemental funding requests (or with other questions pertaining to this DCL) should email the cognizant program officer of the Division supporting the current NSF award with a one-paragraph summary of the request. In that email, it is important to identity the current NSF award number.


There is no deadline for submission of supplemental funding requests. Submissions will be reviewed as they are received. It is expected that supplemental funding requests will be submitted only after the design of the system is sufficiently completed that fabrication will occur within a year of the supplement being granted. Funds will not be granted in the early design stages of a project.


Lead program officers in the participating divisions are:


Susan S. Margulies
Assistant Director, Directorate for Engineering (ENG)

Margaret Martonosi
Assistant Director, Directorate for Computer and Information Science and Engineering (CISE)

Sean L. Jones
Assistant Director, Directorate for Mathematical and Physical Sciences (MPS)