Future of Semiconductors- Teaming for Co-Design Research Capacity (FuSe)

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22-589

Important Information for Proposers

A revised version of the NSF Proposal & Award Policies & Procedures Guide (PAPPG) (NSF 22-1), is effective for proposals submitted, or due, on or after October 4, 2021. Please be advised that, depending on the specified due date, the guidelines contained in NSF 22-1 may apply to proposals submitted in response to this funding opportunity.

Synopsis

The current state of semiconductor microelectronic systems is at a crossroads. Continued advances in the range and capabilities of our technologies as well as reducing their cost of applications across computing, sensing, and communications represent a tremendous opportunity. The technology has expanded following the trends in miniaturization long characterized by Moore’s Law, underpinned by new materials, processes, devices, and architectures. The developments in these underpinning areas have often progressed independent of the application area, delaying their incorporation into the next-generation technologies. Closing that gap between the essential components in the technology stack, from materials through devices to systems, is now required to ensure further progress. The materials, devices and systems need to be co-designed, that is, designed with simultaneous consideration of as many elements of the technology chain as possible, spanning materials, devices, circuits, architectures, software, and applications.

Furthermore, developing a sufficient pool of diverse and multi-disciplinary talent suitable for workforce participation in the US is also essential for the future success of the semiconductor microelectronics field. In addition to fundamental and applied research, rapid developments in the vibrant field of semiconductors also offer new and unique opportunities and challenges when it comes to workforce preparation, education, and broadening participation. Co-design has been widely recognized in government and industry studies as means to accelerate advances in semiconductor technology. A holistic, co-design approach can more rapidly create high-performance, robust, secure, compact, energy-efficient, and cost-effective solutions. The technological challenges that are overcome by co-design approaches include: dramatically reducing the energy consumption of the existing computation and communication systems; reducing the impact of device and system manufacturing on the environment; increasing performance speed and capacity; and developing novel computing systems.

Expediting the next and future generations of semiconductor systems will impact all aspects of modern life and all industries of our economy. The future of semiconductor manufacturing will require the design and deployment of diverse new technologies in materials, chemical and materials processes, devices, architectures through the development of application-driven systems, and engaging the full spectrum of talent in the academic community and industrial sectors. Partnerships between industry and institutions of higher education are essential to spur innovation and technology transfer, to inform the research needs, and to educate future researchers and train the future workforce.

The goal of this solicitation is to cultivate a broad coalition of researchers from across science and engineering communities to utilize a holistic, co-design approach to fundamental research and education and training, to enable rapid progress in new semiconductor technologies. Proposals are sought to support team-formation to articulate co-design visions for the future. Teaming grants are expected to support capacity building across the co-design platform, which positions investigators for future competitive larger research grants and possibly future center activity. Teaming grants can also support catalytic activities that foster stakeholder community networks to develop strategies that address the innovative co-design capacity of the U.S. for future semiconductors at the national research center level. Teaming grants prepares groups of complimentary researchers to respond to future calls for co-design research and potentially centers.

Initially, team formation is directed to the following three research areas identified for support in FY 2022 under this solicitation, as described in greater detail below:

·         Collaborative Research in Domain-Specific Computing

·         Advancing Function and Achieving High-Performance from Heterointegration

·         New Materials for Energy Efficient, Enhanced-performance and Sustainable Semiconductor-based Systems

Future of Semiconductor Teaming Grants (FuSe-TG) - Awards will provide up to two years of support for up to $100,000 per participating organization on the proposal with a minimum of three organizations. Proposals can address any of the three topic areas above, or another research problem requiring co-design in the broad area of semiconductors. The Teaming Grants are intended to stimulate research capacity through multidisciplinary team building and the development of high-impact, fundamental research concepts. The Teaming Grants are appropriate for supporting a range of planning activities intended to identify, compose, educate, and foster a convergent research team that can effectively integrate multiple disciplinary perspectives, explore the co-design research platform, hone research gaps, questions, and hypotheses, and build synergistic collaborations that enhance or create a combined capacity to address FuSe co-design research challenges. Activities within the scope of this solicitation include but are not limited to, travel, student support, multidisciplinary workshops, data collection, preliminary experiments, and pilots. At the conclusion of any FuSe-TG, teams may have identified additional members for covering complementary areas and should be prepared to pursue a potential future well-defined research challenge ranging in scope and scale from multi-participant, interdisciplinary research grants up to future co-design centers. For example, Future of Semiconductor Centers for Co-Design may serve as national nexus points for collaborative efforts spanning institutions of higher education, federal agencies, semiconductor industry sectors including foundries, and other nonprofits/foundations in such areas. They would be directed towards the acceleration of the transition of innovations throughout the technology stack from materials to applications impacting many economic sectors, and nurture and grow the next generation of talent. FuSe-TG proposals for co-design centers must identify critical needs for solutions and address strategies guiding the proposed teaming activities. The anticipated outcomes for FuSe-TG award for co-design centers must include increased capacity of the semiconductor research and education, strengthened partnerships with industry and stakeholders, and broadened participation, which enables the teams to be better equipped to tackle, in the future, a center-scale, convergent, co-design research effort with large societal impact at the national level or in a global context.

For teaming grant activities, interdisciplinary teams commensurate with the scope of the proposed research, education plan, and budget are required. Proposals led by or including minority-serving institutions (https://www2.ed.gov/about/offices/list/ocr/edlite-minorityinst.html) are encouraged. Proposals must include expertise among the team members to carry out the proposed research, education, and workforce development activities. A diverse team and convergence research are expected.

Realizing the benefits of the fundamental co-design research approach supported under this solicitation requires the simultaneous education of a skilled technical workforce to transition new discoveries into U.S.-based industries. The National Science Board emphasizes this perspective in its report, "The Skilled Technical Workforce: Crafting America's Science and Engineering Enterprise.” Therefore, proposers responding to this solicitation must include within the Project Description a section titled “Education and Workforce Development Plan” that describes proposed efforts to equip students and upskill the existing workforce needed for future technologies. It should also include an evaluation component, led by an appropriate expert, to assess the effectiveness of approach. The Education and Workforce Development Plan should describe the approaches developed by the team for education and training which are innovative, evidence-based, aligned with changing workforce and research needs, transferable, and dedicated to developing diverse and versatile professionals to support the semiconductor field. The plan should describe the population(s) to be served and specify the anticipated numbers of trainees supported. The plan should also include a timeline of progressive training elements.

Program contacts

Sankar Basu
(CISE/CCF)
fuse@nsf.gov (703) 292-7843 CISE/CCF
Geoffrey Brown
(TIP)
fuse@nsf.gov (703) 292-4749 TIP/ITE
Erik N. Brunvand
(CISE/CNS)
fuse@nsf.gov (703) 292-2767 CISE/CNS
James H. Edgar
(MPS/EPM)
fuse@nsf.gov (703) 292-2053
Ruyan Guo
(ENG/ECCS)
fuse@nsf.gov (703) 292-7718 ENG/ECCS
George M. Janini
(MPS/CHE)
fuse@nsf.gov (703) 292-4971 MPS/CHE
Thomas F. Kuech
(ENG/CMMI)
fuse@nsf.gov (703) 292-2218 ENG/CMMI
Vinod K. Lohani
(EHR/DGE)
fuse@nsf.gov (703) 292-2330 EHR/DGE
Rosa Lukaszew
(ENG/ECCS)
fuse@nsf.gov (703) 292-8103 ENG/ECCS
Eleanor Sayre
(EHR/DUE)
fuse@nsf.gov (703) 292-2330 EHR/DUE
Birgit Schwenzer
(MPS/DMR)
fuse@nsf.gov (703) 292-4771 MPS/DMR

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